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ST10F167
16-bit MCU with 128KByte FLASH memory
DATA SHEET
P.4 P.1 P.0
GPT2/GPT1
ASC usart
10-Bit ADC
CAPCOM2
CAPCOM1 P.8
PWM
SSC
q 16-bit CPU with 4 stage pipeline q 100ns instruction cycle time at 20MHz CPU clock q 500ns multiplication (16*16 bit) q 1s division (32/16 bit) q Enhanced boolean bit manipulation facilities q Additional instructions to support HLL and operating systems q Single-cycle context switching support
128Kbyte FLASH
s High Performance CPU
CPU-Core
PEC
Internal RAM Wdog
XRAM Interrupt Controller CAN
OSC.
P.7
P.2
q 2K bytes on-chip internal RAM q 2K bytes on-chip Extension RAM q 128K bytes on-chip FLASH memory q FLASH with 4 independently erasable banks
EBC
s Memory organization
BRG P.3
BRG
P.6
P.5
s A/D converter
q 16-channel 10-bit 9.7s conversion time.
s Fast and fl exible bus
q Programmable external bus characteristics for different address ranges q 8-Bit or 16-Bit external data bus. q Multiplexed or de-multiplexed external address/data buses q Five programmable chip-select signals. q Hold and hold-acknowledge bus arbitration support
s Clock Generation
q On-chip PLL. q Direct clock input
s Up to 111 General Purpose I/O Lines s Programmable threshold (hysteresis) s Idle and power down modes
q Idle current <70mA q Power down supply current <100A.
s Fail-safe protection
q Programmable watchdog timer
s 4-Channel PWM Unit s Serial channels
q Synchronous/asynch serial channel. q High speed synchronous channel
s On-chip CAN 2.0B Interface s On-chip bootstrap loader s Interrupt
q 8-channel PEC for single cycle, interrupt driven data transfer q 16-priority-level interrupt system with 56 sources, sample-rate down to 50ns
s Electrical characteristics
q Power - 5 volt +/- 10%
s Development support
q C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
s Timers
q Two multi-functional general-purpose timer units with 5 timers q Two 16-bit capture/compare units
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s Package option
q 144-Pin PQFP Package 10 September 98
DATA SHEET
ST10F167
Table of Contents
1 2 3 4 5 5.1 5.2
5.2.1
Introduction - - - - - - - - - - - - - - - - - - - - - - - - - - 4 Pin Data - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5 Functional Description - - - - - - - - - - - - - - - - - - - 12 Memory Organization - - - - - - - - - - - - - - - - - - - - 13 Flash Memory - - - - - - - - - - - - - - - - - - - - - - - - 14 Flash programming and erasing - - - - - - - - - - - - - - - 15 Flash Control Register (FCR) - - - - - - - - - - - - - - - - - 15
Flash memory security - - - - - - - - - - - - - - - - - - - - - - - - 18
6 7 8 9 10 10.1 10.2 11 12 13 14 14.1 14.2
External Bus Controller - - - - - - - - - - - - - - - - - - - 20 Central Processing Unit (CPU) - - - - - - - - - - - - - - - 21 Interrupt System - - - - - - - - - - - - - - - - - - - - - - 22 Capture/compare (CAPCOM) Units - - - - - - - - - - - - - 26 General Purpose Timer (GPT) Unit - - - - - - - - - - - - - 28 GPT1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 28 GPT2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 29 PWM Module - - - - - - - - - - - - - - - - - - - - - - - - 31 Parallel Ports - - - - - - - - - - - - - - - - - - - - - - - - 32 A/D Converter - - - - - - - - - - - - - - - - - - - - - - - - 33 Serial Channels - - - - - - - - - - - - - - - - - - - - - - - 34 ASCO - - - - - - - - - - - - - - - - - - - - - - - - - - - - 34 High speed synchronous serial channel (SSC) - - - - - - - - 35
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DATA SHEET
ST10F167 15 16 17 18 19 20 20.1 20.2 20.3 20.4 20.5
20.5.1 20.5.2 20.5.3 20.5.4 20.5.5 20.5.6 20.5.7 20.5.8 20.5.9 20.5.10
Can Module - - - - - - - - - - - - - - - - - - - - - - - - - 36 Watchdog Timer Instruction Set - - - - - - - - - - - - - - - - - - - - - - 37 - - - - - - - - - - - - - - - - - - - - - - - 38
Bootstrap Loader - - - - - - - - - - - - - - - - - - - - - - 40 Special Function Registers - - - - - - - - - - - - - - - - - 40 Electrical Characteristics - - - - - - - - - - - - - - - - - - 48 Absolute maximum ratings - Parameter interpretation - - DC Characteristics - - - - - A/D Converter Characteristics AC Characteristics - - - - - Test waveforms - - - - Definition of internal timing Direct Drive - - - - - - Phase locked loop - - - External clock drive XTAL1 Memory cycle variables - Multiplexed Bus - - - - Demultiplexed Bus - - - CLKOUT and READY - External Bus Arbitration - -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
48 48 49 52 54
54 54 55 56 57 58 58 65 71 73
21 22 23
Package Mechanical Data - - - - - - - - - - - - - - - - - - 76 Ordering Information - - - - - - - - - - - - - - - - - - - - 76 Revision History - - - - - - - - - - - - - - - - - - - - - - 77
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DATA SHEET
ST10F167
1
Introduction
The ST10F167 is a new derivative of the ST Microelectronics 16-bit single-chip CMOS microcontrollers. It combines high CPU performance with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed RAM and clock generation via PLL.
VDD
XTAL1 XTAL2 RSTIN RSTOUT VAREF VAGND NMI EA READY ALE RD WR/WRL Port 5 16-bit
VSS
Port 0 16-bit Port 1 16-bit Port 2 16-bit
ST10F167
Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit
Figure 1 Logic symbol
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2
P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO VDD VSS P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28I0 P7.5/CC29I0 P7.6/CC30I0 P7.7/CC31I0 P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9
Pin Data
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
ST10F167
DATA SHEET
Figure 2 Pin out
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 POH.0/AD8 POL.7/AD7 POL.6/AD6 POL.5/AD5 POL.4/AD4 POL.3/AD3 POL.2AD2 POL.1/AD1 POL.0/AD0 EA ALE READY WR/WRL RD VSS VDD P4.7/A23 P4.6/A22/CAN_TXD P4.5/A21/CAN_RXD P4.4/A20 P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 VPP VSS VDD P3.15/CLKOUT P3.13/SCLK P3.12/BHE/WRH P3.11/RXD0 P3.10/TXD0 P3.9/MTSR P3.8/MRST P3.7/T2IN P3.6/T3IN
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VAREF VAGND P5.10/AN10/T6EUD P5.11/AN11/T5EUD P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4EUD P5.15/AN15/T2EUD VSS VDD P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO VSS VDD P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IOEX2IN P2.11/CC11IOEX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN/T7IN P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN VSS VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS NMI RSTOUT RSTIN VSS XTAL1 XTAL2 VDD P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VSS VDD P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 POH.7/AD15 POH.6/AD14 POH.5/AD13 POH.4/AD12 POH.3/AD11 POH.2/AD10 POH.1/AD9 VSS VDD
ST10F167
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DATA SHEET
ST10F167
Symbol P6.0 - P6.7
Pin 1-8
Input(I)/ Output(O) I/O
Function Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The following Port 6 pins also serve for alternate functions: P6.0 CS0 Chip Select 0 Output ... ... ... P6.4 CS4 Chip Select 4 Output P6.5 HOLD External Master Hold Request Input P6.6 HLDA Hold Acknowledge Output P6.7 BREQ Bus Request Output Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 8 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out ... ... ... P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 7 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: P7.0 POUT0 PWM Channel 0 Output ... ... ... P7.3 POUT3 PWM Channel 3 Output P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out ... ... ... P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out
1 ... 5 6 7 8 P8.0 - P8.7 9 - 16
O ... O I O O I/O
9 ... 16 P7.0 - P7.7 19 - 26
I/O ... I/O I/O
19 ... 22 23 ... 26
O ... O I/O ... I/O
Table 1 Pin description
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DATA SHEET
ST10F167
Symbol P5.0P5.15
Pin 27 - 36 39 - 44
Input(I)/ Output(O) I I
Function Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out ... ... ... P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out, EX0IN Fast External Interrupt 0 Input ... ... ... P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out, EX7IN Fast External Interrupt 7 Input T7IN CAPCOM2 Timer T7 Count Input
39 40 41 42 43 44 P2.0P2.15 47 - 54 57 - 64
I I I I I I I/O
47 ... 54 57 ... 64
I/O ... I/O I/O I ... I/O I I
Table 1 Pin description
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DATA SHEET
ST10F167
Symbol P3.0P3.13, P3.15
Pin 65 - 70, 73 - 80, 81
Input(I)/ Output(O) I/O I/O I/O
Function Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE Ext. Memory High Byte Enable Signal, WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line P4.5 A21 Segment Address Line, CAN_RxD CAN Receive Data Input P4.6 A22 Segment Address Line, CAN_TxD CAN Transmit Data Output P4.7 A23 Most Significant Segment Addr. Line
65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 P4.0 - P4.7 85 - 92
I O I O I I I I I/O I/O O I/O O O I/O O I/O
85 90 91 92
O O I O O O
Table 1 Pin description
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DATA SHEET
ST10F167
Symbol RD
Pin 95
Input(I)/ Output(O) O
Function External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the ST10F167 to begin instruction execution out of external memory. A high level forces execution out of the internal Flash Memory. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15
WR/ WRL
96
O
READY
97
I
ALE
98
O
EA
99
I
PORT0: P0L.0P0L.7 P0H.0P0H.7
I/O 100-107 108, 111-117
Table 1 Pin description
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DATA SHEET
ST10F167
Symbol PORT1: P1L.0 - P1L.7, P1H.0 P1H.7
Pin
Input(I)/ Output(O) I/O
Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4 CC24IO CAPCOM2: CC24 Capture Input P1H.5 CC25IO CAPCOM2: CC25 Capture Input P1H.6 CC26IO CAPCOM2: CC26 Capture Input P1H.7 CC27IO CAPCOM2: CC27 Capture Input XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F167. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. Internal Reset Indication Output. This pin is set to a low level when the part is executing, either a hardware, a software or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F167 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Reference voltage for the A/D converter. Reference ground for the A/D converter.
118 - 125 128 - 135
132 133 134 135 XTAL1 XTAL2 138 137
I I I I I O
RSTIN
140
I
RSTOUT
141
O
NMI
142
I
VAREF VAGND
37 38
-
Table 1 Pin description
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DATA SHEET
ST10F167
Symbol VPP
Pin 84
Input(I)/ Output(O) -
Function Flash programming voltage. This pin accepts the programming voltage for the on-chip flash EPROM of the ST10F167. Digital Supply Voltage for internal circuitry: + 5 V during normal operation and idle mode. 2.5 V during power down mode Digital Supply Voltage for port drivers: + 5 V during normal operation and idle mode
VDD
46, 82, 136
-
17, 56, 72, 93, 109,126 ,144 VSS 45, 83, 139 18, 55, 71, 94, 110,127 ,143
-
-
Digital Ground for internal circuitry.
-
Digital Ground for port drivers.
Table 1 Pin description
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ST10F167
3
Functional Description
The architecture of the ST10F167 combines advantagesof both RISC and CISC processors and an advanced peripheral subsystem. The following block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F167.
16 Internal FLASH Memory 32
CPU-Core
16
Internal RAM
16 PEC XRAM 16 Interrupt Controller 16 CAN
Watchdog
OSC.
Port 4 Port 1 Port 0
GPT1
ASC usart
CAPCOM2
10-Bit ADC
PWM
16 16
External Bus Controller
CAPCOM1
SSC
GPT2
Port 2 8
16
8
BRG Port 3 15
BRG Port 7 8 Port 8
Port 6 8
Port 5 16
Figure 3 Block diagram
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ST10F167
4
Memory Organization
The memory space of the ST10F167 is configured in a Von-Neumann architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The ST10F167 provides 128KBytes of on-chip flash memory. 2 KBytes of on-chip Internal RAM stores user defi ned variables for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for other/future members of the ST10 family. 2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code. The XRAM is accessed like external memory and cannot be used for the system stack or register banks, and is not bit-addressable. The XRAM allows 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.
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DATA SHEET
ST10F167
5
Flash Memory
The ST10F167 provides 128KBytes of on-chip, electrically erasable and re-programmable Flash EPROM. The fl ash memory is organized in 32 bit wide blocks. Double word instructions can be fetched in one machine cycle. The fl ash memory can be used for both code and data storage. It is into four banks of sizes 8K, 24K, 48K and 48Kbytes. Each of these banks can be erased independently This prevents unnecessary re-programming of . the whole fl ash memory when only a partial re-programming is required. The fi rst 32K bytes of the FLASH memory are located in segment 0 (0h to 007FFFh) during reset, and include the reset and interrupt vectors. The rest of the FLASH memory is mapped in segments 1 and 2 (018000h to 02FFFFh). For fl exibility, the fi rst 32K bytes of the FLASH memory may be remapped to segment 1 (010000h to 017FFFh) during initialization. This allows the interrupt vectors to be programmed from the external memory, while retaining the common routines and constants that are programmed into the FLASH memory.
Bank 0 1 2 3 Addresses (Segment 0) 000000h to 07FFFh and 018000h to 01BFFFh 01C000h to 027FFFh 028000h to 02DFFFh 02E000h to 02FFFFh Size (bytes) 48K 48K 24K 8K
Table 2 Flash memory bank addresses
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ST10F167
5.1
Flash programming and erasing
The FLASH memory is programmedusing the PRESTO F ProgramWrite algorithm. Erasure of the FLASH memory is performed in the program mode using the PRESTO F Erase algorithm. Timing of the Write/Erase cycles is automatically generated by a programmable timer and completion is indicated by a fl ag. A second flag indicates that the VPP voltage was correct for the whole programming cycle. This guarantees that a good write/erase operation has been carried out.
Parameter Word Programming Time Bank Erasing Time Endurance Flash Vpp Units sec sec cycles volts 11.4 Min 12.8 Typical 12.8 0.5 1000 12.6 Max 1250 30
Table 3 Flash Parameters
5.2
Flash Control Register (FCR)
In the standard operation mode, the FLASH memory can be accessed in the same way as the normal mask-programmable on-chip ROM. All, appropriate, direct and indirect addressing modes can be used for reading the FLASH memory. All programming or erase operations are controlled via a 16-bit register, the FCR. The FCR is not an SFR or GPR. To prevent inadvertent writing to the FLASH memory, the FCR is locked and inactive during the standard operation mode. The FLASH memory writing mode must be entered, before a valid access to the FCR is provided. This is done via a special key code instruction sequence. The FCR is virtually mapped into the active address space of the Flash memory. It can only be accessed with direct 16-bit (mem) addressing modes. Since the FCR is neither byte, nor bit-addressable, only word operand instructions can be used for FCR accesses. By default, the FCR can be accessed with any even address from 000000h to 07FFFEh and 018000h to 02FFFEh. If the first 32K byte Block of the FLASH memory is mapped to segment 1, the corresponding even FCR addresses are 010000h to 017FFEh. Note that DPP referencing and DPP contents must be considered for FCR accesses. If an FCR access is attempted via an odd address, an illegal operand access hardware trap will occur. FCR Flash Control Register: Reset Condition: 0000h (Read)
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ST10F167
Bit number & name b15 = FWMSET Flash Writing Mode Set.
Description This bit is set to "1" automatically once the Flash writing mode is entered. To exit from the Flash writing mode, FWMSET must be set to "0". Since only word values can be written to FCR, care must be taken that FWMSET is not cleared inadvertently. Therefore, for any command written to FCR (except for the return to the Flash standard mode), FWMSET must be set to "1". Reset condition of FWMSET is "0". These bits are reserved for future development, they must be written to "0". Select the Flash memory bank to be erased. The physical addresses of bank 0 depends on the which Flash memory map has been chosen. In Flash operating modes, other than the erasing mode, these bits are not signifi cant. At reset BE1,0 are set to "00". Determines the word width used for programming operations: 16-bit (WDWW = 0) or 32-bit (WDWW = "1"). In Flash operation modes, other than the programming mode, this bit is not signifi cant. At reset, WDWW is set to "0". Control the width (TPRG) of the programming or erase pulses applied to the Flash memory cells during the operation. TPRG varies in an inverse ratio to the clock frequency. To avoid putting the Flash memory under critical stress conditions, the width of one single programming or erase pulse and the programming or erase time, must not exceed defi ned values. Thus the maximum number of programming or erase attempts, depends on the system clock frequency.
b14-b10
b9-b8 = BE0,1 Bank erase select.
b7 = WDWW Word/double word write. b6-b5 = CKCTL0,1 Flash Timer Clock Control.
RESET state: 00. b4 = VPPRIV Read-only bit refl ects the state of the VPP voltage in the Flash writing mode. If VPPRIV is set to "0", this indicates that V PP is below the threshold necessary for reliable programming. The normal reaction to this indication is to check the VPP power supply and to then repeat the intended operation. If the VPP voltage is above a suffi cient margin, VPPRIV will be set to "1". The reset state of the VPPRIV bit depends on the state of the external VPP voltage at the VPP pin.
VPP Revelation bit.
Table 4 Flash control register bit definition
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Bit number & name b3 = FCVPP Flash VPP control bit.
Description Read-only bit indicates that the VPP voltage fell below the valid threshold value during a Flash programming or erase operation. If FCVPP is set to "1" after such an operation has fi nished, it can mean that the operation was not successful. The VPP power supply should be checked and the operation repeated. If FCVPP is set to "0", no critical discontinuity in VPP occurred. At reset FCVPP is set to "0". Read-only bit indicates that a Flash programming or erase operation is in progress. FBUSY is set to "1" by hardware, as soon as the programming or erase command is given. At reset FBUSY is set to "0". Note that this bit position is also occupied by the write-only bit RPROT. This bit set at 1, anded with the OTP protection bit, disables any access to the Flash, by instructions fetched from the external memory space, or from the internal RAM. This write-only bit, is only signifi cant if the general Flash memory protection is enabled. If the protection is enabled, the setting of RPROT determines whether the Flash protection is active (RPROT="1") or inactive (RPROT="0"). RPROT is the only FCR bit which can be modifi ed even in the Flash standard operation mode, but only by an instruction executed from the Flash memory itself. At reset, RPROT is set to "1". Note that this bit position is also occupied by the read-only bit FBUSY. Selects the Flash write operation to be performed: erase (FEE="1") or programming (FEE="0"). Together with bits FWE and FWMSET, bit FEE determined the operation mode of the Flash memory. Note that setting bits FWE and FEE causes the corresponding Flash operation mode to be selected but does not launch the execution of the selected operation. If bit FWE was set to "0", the setting of FEE is insignifi cant. At reset, FEE is set to "0". This bit determines whether FLASH write operations are enabled (FWE=1) or disabled (FWE=0). By defi nition, a FLASH write operation can be either programming or erasure. Together with bits FEE and FWMSET, bit FWE determines the operation mode of the Flash memory. Note that setting bits FWE and FEE causes the corresponding Flash operation mode to be selected but does not launch the execution of the selected operation. If bit FWE was set to "1", any read access on a Flash memory location means a particular program-verify or erase-verify read operation. Flash write operations are disabled at reset.
b2 = FBUSY Flash busy bit.
b2 = RPROT Protection enable bit.
b1 = FEE Flash erase/program selection.
b0 = FWE Flash write/read enable.
Table 4 Flash control register bit definition
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5.2.1 Flash memory security
Security and reliability have been enhanced by built-in features: a key code sequence is used to enter the Write/Erase mode preventing false write cycles, a programmable option (set by the programming board) prevents access to the FLASH memory from the internal RAM or from External Memory. If the security option is set, the FLASH memory can only be accessed from a program within the FLASH memory area. This protection can only be disabled by instructions executed from the FLASH memory.
=0
PCOUNT=PNmax?
PCOUNT=PCOUNT+1
VR02057A
Figure 4 PRESTO F write algorithm
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=0
PCOUNT=ENmax?
PCOUNT=PCOUNT+1
VR02057B
Figure 5 PRESTO F erase algorithm
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6
External Bus Controller
All of the external memory accesses are performed by the on-chip External Bus Controller (EBC). It can be programmed either to single chip mode when no external memory is required, or to one of four different external memory access modes:
* 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed * 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed * 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed * 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/ output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable. This gives the choice of a wide range of different types of memories and external peripherals. In addition, different address ranges may be accessed with different bus characteristics. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported via a particular `Ready' function. A HOLD/HLDA protocol is available for bus arbitration. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines. If an address space of 16 MBytes is used, it outputs all 8 address lines.
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7
Central Processing Unit (CPU)
CPU
SP STKOV STKUN Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs MDH MLD Mul./Div.-HW Bit-Mask Gen. R15 Internal General ALU 16-Bit Barrel-Shift Context Ptr ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. Purpose Registers R15 RAM 2KByte 16
FLASH ROM
32
R0 16 R0
Figure 6 CPU block diagram The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU). Dedicated SFRs have been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F167's instructions can be executed in one instruction cycle which requires 100ns at 20MHz CPU clock. For example, shift and rotate instructions are always processed in one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized for speed: branches in 2 cycles, a 16 X 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. The `Jump Cache' pipeline optimization, reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. The CPU includes an actual register context. This consists of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.
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8
Interrupt System
With an interrupt response time from 250ns to 600ns (in the case of internal program execution), the ST10F167 reacts quickly to the occurrence of non-deterministic events The architecture of the ST10F167 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In a standard interrupt service, program execution is suspended and a branch to the interrupt vector table is performed. For a PEC service, just one cycle is `stolen' from the current CPU activity. A PEC service is a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is decremented for each PEC service, except for the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are suited to, for example, the transmission or reception of blocks of data. The ST10F167 has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request fl ag, an interrupt enable fl ag and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The table below shows all of the possible ST10F167 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 Request Flag CC0IR CC1IR Enable Flag CC0IE CC1IE Interrupt Vector CC0INT CC1INT Vector Location 00'0040h 00'0044h Trap Number 10h 11h
Table 5 List of interrupt sources
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Source of Interrupt or PEC Service Request CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30
Request Flag CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR
Enable Flag CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE
Interrupt Vector CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT
Vector Location 00'0048h 00'004Ch 00'0050h 00'0054h 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h 00'00C8h 00'00CCh 00'00D0h 00'00D4h 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00E0h 00'0110h 00'0114h
Trap Number 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 44h 45h
Table 5 List of interrupt sources
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Source of Interrupt or PEC Service Request CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 CAN Interface X-Peripheral Node X-Peripheral Node PLL Unlock
Request Flag CC31IR T0IR T1IR T7IR T8IR T2IR T3IR T4IR T5IR T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR
Enable Flag CC31IE T0IE T1IE T7IE T8IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE
Interrupt Vector CC31INT T0INT T1INT T7INT T8INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT
Vector Location 00'0118h 00'0080h 00'0084h 00'00F4h 00'00F8h 00'0088h 00'008Ch 00'0090h 00'0094h 00'0098h 00'009Ch 00'00A0h 00'00A4h 00'00A8h 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch
Trap Number 46h 20h 21h 3Dh 3Eh 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 47h 2Bh 2Ch 2Dh 2Eh 2Fh 3Fh 40h 41h 42h 43h
Table 5 List of interrupt sources
Note
Two X-Peripheral nodes can accept interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
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The ST10F167 identifies and to processes exceptions or error conditions that arise during run-time, `Hardware Traps'. Hardware traps cause an immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap fl ag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts The table below shows all of the possible exceptions or error conditions that can arise during run-time.
Trap Flag Trap Vector Vector Location Trap Number Trap Priority
Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overfl ow Class A Hardware Traps: Non-Maskable Interrupt Stack Overfl ow Stack Underfl ow Class B Hardware Traps: Undefi ned Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps: TRAP Instruction
RESET RESET RESET
00'0000h 00'0000h 00'0000h
00h 00h 00h
III III III
NMI STKOF STKUF
NMITRAP STOTRAP STUTRAP
00'0008h 00'0010h 00'0018h
02h 04h 06h
II II II
UNDOPC PRTFLT ILLOPA ILLINA ILLBUS
BTRAP BTRAP BTRAP BTRAP BTRAP
00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [2Ch -3Ch]
0Ah 0Ah 0Ah 0Ah 0Ah [0Bh - 0Fh]
I I I I I
Any Any [00'0000h- [00h - 7Fh] 00'01FCh] in steps of 4h
Current CPU Priority
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9
Capture/compare (CAPCOM) Units
The CAPCOM units support generation and control of timing sequences on up to 32 channels. It has a maximum resolution of 400 ns at 20MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers, provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several pre-scaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Both of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin (except for CC24...CC27) to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specifi c interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/ compare register, specific actions will be taken, based on the selected compare mode.
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Compare Modes Mode 0
Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overfl ow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.
Mode 1
Mode 2
Mode 3
Double Register Mode
Table 6 Compare modes The input frequencies fTx for Tx are determined as a function of the CPU clocks. The formulas are detailed in the user manual. The timer input frequencies, resolution and periods which result from the selected pre-scaler option in TxI when using a 20MHz CPU clock are listed in the table below. The numbers for the timer periods are based on a reload value of 0000H. Note that some numbers may be rounded to 3 significant fi gures.
fCPU = 20MHz Pre-scaler for fCPU Input Frequency Resolution Period Timer Input Selection TxI 000B 8 2.5 MHz 400ns 26.2ms 001B 16 1.25 MHz 800ns 52.4ms 010B 32 625 kHz 1.60s 105ms 011B 64 313 kHz 3.20s 210ms 100B 128 156 kHz 6.40s 419ms 101B 256 78.1 kHz 12.8s 839ms 110B 512 39.1 kHz 25.6s 1.68s 111B 1024 19.5 kHz 51.2s 3.36s
Table 7 CAPCOM timer input frequencies, resolution and periods
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10 General Purpose Timer (GPT) Unit
The GPT unit is a flexible multifunctional timer/counter structure. It may be used for many different time-related tasks such as: event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer, in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module.
10.1 GPT1
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation: timer, gated timer, and counter mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. counter mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. Each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 8 GPT1 timer input frequencies, resolution and periods lists the timer input frequencies, resolution and periods for each pre-scaler option at 25 MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode.
fCPU = 20MHz Timer Input Selection T2I / T3I / T4I 000B Pre scaler Input Frequency Resolution Period 8 2.5 MHz 400ns 26.2ms 001B 16 1.25 MHz 800ns 52.4ms 010B 32 625 kHz 1.60s 105ms 011B 64 313 kHz 3.20s 210ms 100B 128 156 kHz 6.40s 419ms 101B 256 78.1 kHz 12.8s 839ms 110B 512 39.1 kHz 25.6s 1.68s 111B 1024 19.5 kHz 51.2s 3.36s
Table 8 GPT1 timer input frequencies, resolution and periods The count direction (up/down) for each timer is programmable by software or may be altered dynamically by an external signal on a port pin (TxEUD) to facilitate, for example, position tracking. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/ underfl ow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.
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In addition to their basic operating modes, timers T2 and T4 may be confi gured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4, triggered, either by an external signal, or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.
10.2 GPT2
The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported by the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. Table 9 GPT2 timer input frequencies, resolution and period lists the timer input frequencies, resolution and periods for each pre-scaler option at 25 MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode.
fCPU = 20MHz
Timer Input Selection T5I / T6I 000B Pre-scaler factor Input Frequency Resolution Period 4 5 MHz 200ns 001B 8 2.5 MHz 400ns 010B 16 1.25 MHz 800ns 52.4ms 011B 32 625 kHz 1.60s 105ms 100B 64 313 kHz 3.20s 210ms 101B 128 156 kHz 6.40s 419ms 110B 256 78.1 kHz 12.8s 839ms 111B 512 39.1 kHz 25.6s 1.68s
13.11ms 26.2ms
Table 9 GPT2 timer input frequencies, resolution and period
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T2EUD
U/D GPT1 Timer T2 2n n=3...10 Interrupt Request
CPU Clock T2IN
T2 Mode Control
Reload Capture
CPU Clock
2n n=3...10
T3EUD
T3 Mode Control
T3OUT GPT1 Timer T3 U/D T3OTL
T3IN
T4IN CPU Clock
T4 Mode Control 2n n=3...10
Capture Reload
Interrupt Request Interrupt Request
GPT1 Timer T4 U/D
T4EUD
Figure 7 Block diagram of GPT1
T5EUD CPU Clock T5IN U/D 2n n=2...9
T5 Mode Control
GPT2 Timer T5 Clear Capture
Interrupt Request
CAPIN GPT2 CAPREL
Interrupt Request
Reload
Interrupt Request
T6IN CPU Clock T6EUD 2n n=2...9
T6 Mode Control
Toggle FF GPT2 Timer T6 U/D T60TL T6OUT to CAPCOM Timers
Figure 8 Block diagram of GPT2
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11 PWM Module
The Pulse Width Modulation unit can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. The table below shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests.
Mode 0 CPU Clock/1 CPU Clock/64 Mode 1 CPU Clock/1 CPU Clock/64 Resolution 50ns 3.2ns Resolution 50ns 3.2ns 8-bit 78.13 KHz 1.221KHz 8-bit 39.06KHz 610.4Hz 10-bit 19.53KHz 305.2 Hz 10-bit 9.766KHz 152.6 Hz 12-bit 4.883KHz 76.29Hz 12-bit 2.441KHz 38.15Hz 14-bit 1.221KHz 19.07Hz 14-bit 610.4Hz 9.537Hz 16-bit 0.305KHz 4.768Hz 16-bit 152.6Hz 0Hz
Table 10 PWM unit frequencies and resolution at 20MHz CPU clock
Figure 9 Block diagram of PWM module
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12 Parallel Ports
The ST10F167 provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when confi gured as inputs. The output drivers of three I/O ports can be confi gured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are confi gured as inputs. The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like). The special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64KBytes of memory.Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.
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13 A/D Converter
A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integratedon-chip for analog signal measurement. It uses a successive approximation method. The sample time (for loading the capacitors) and conversion time is programmable and can be modified for the external circuitry. Overrun error detection/protection is provided through the conversion result register (ADDAT). When the result of a previous conversion has not been read from the result register at the time the next conversion is complete, either an interrupt request is generated, or the next conversion is suspended, until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F167 supports four different conversion modes.
* Single Channel conversion mode: The analog level on a specified channel is sampled
once and converted to a digital result.
* Single Channel Continuous mode: The analog level on a specified channel is repeatedly
sampled and converted without software intervention.
* Auto Scan mode: The analog levels on a prespecified number of channels are
sequentially sampled and converted.
* Auto Scan Continuous mode: the number of prespecified channels is repeatedly
sampled and converted. In addition, channel injection mode injects a channel into a running sequence without disturbing this sequence. The peripheral event controller stores the conversion results in memory without entering and exiting interrupt routines for each data transfer. The following table shows the ADC unit conversion clock, sample clock and complete conversion times.
ADCTC 00 01 10 11 Conversion clock tcc 0.6s reserved 2.4s 1.2s ADSTC 00 01 10 11 Sample clock tsc 0.6s reserved 9.6s 9.6s 52.9s 36.1s Complete conversion 9.7s
Table 11 ADC sample clock and complete conversion times
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After each reset and also during normal operation, the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to the changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle and do not affect the normal operation of the A/D converter.
14 Serial Channels
Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces. An Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
14.1 ASCO
ASC0 supports full-duplex asynchronous communication up to 625 KBaud and half-duplex synchronous communication up to 2.5 Mbaud @ 20MHz system clock. The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20MHz system clock. For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. The table below lists various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate.
S0BRS = `0', fCPU = 20MHz Baud Rate Deviation Error (Baud) 625000 56000 38400 19200 9600 4800 2400 1200 600 76 0.0% +1.5% +1.7% +1.7% +0.2% +0.2% +0.2% +0.2% +0.1% +0.4% / -7.0% / -4.3% / -1.4% / -1.4% /-0.6% / -0.2% / -0.0% / -0.0% / 0.4% Reload Value 0000H 000FH / 0010H 001FH / 0020H 0040H/ 0041H 0081H / 0082H 0103H / 0104H 0207H / 0208H 0410H / 0411H S0BRS = `1', fCPU = 20MHz Baud Rate Deviation Error (Baud) 416666 0.0% +6.3% +8.5% +3.3% +0.9% +0.9% +0.4% +0.1% +0.1% +0.0% +1.7% / -7.0% / -1.4% / -1.4% / -1.4% / -0.2% / -0.2% / -0.2% / -0.1% / 0.0% / 1.7% Reload Value 0000H 0006H / 0007H 0009H / 000AH 0014H / 0015H 002AH / 002BH 0055H / 0056H 00ACH / 00ADH 015AH / 015BH 02B5H / 02B6H 15B2H / 15B3H 1FFFH / 1FFFH
000AH / 000BH 56000 38400 19200 9600 4800 2400 1200 600
1FFFH / 1FFFH 75 50
Table 12 Commonly used baud rates by reload value and deviation errors
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Note The deviation errors given in the table above are rounded. Using a baudrate crystal will provide correct baudrates without deviation errors.
For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate.
14.2 High speed synchronous serial channel (SSC)
The High-Speed Synchronous Serial Interface SSC provides fl exible high-speed serial communication between the ST10F167 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication; The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. The serial channel SSC has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent from the timers. SSCBR is the dual-function Baud Rate Generator/Reload register. The table below lists some possible baud rates against the required reload values and the resulting bit times for a 20MHz CPU clock.
Baud Rate Reserved use a reload value > 0. 5 3.3 2.5 2 1 100 10 1 152.6 MBaud MBaud MBaud MBaud MBaud KBaud KBaud KBaud Baud Bit Time --200 303 400 500 1 10 100 1 6.6 ns ns ns ns s s s ms ms Reload Value 0000H 0001H 0002H 0003H 0004H 0009H 0063H 03E7H 270FH FFFFH
Table 13 Synchronous baud rate and reload values
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15 Can Module
The integrated CAN-Module performs the autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active). The on-chip CAN-Module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The module provides full CAN functionality for up to 15 message objects. Message object 15 may be confi gured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifi ers in Full CAN mode and also allows to disregard a number of identifi ers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The CAN-Module uses two pins to interface to a bus transceiver.
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16 Watchdog Timer
The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip's start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL. Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. The table below shows the watchdog timer range for 20MHz CPU clock. Some numbers are rounded to 3 significant digits.
Prescaler for fCPU 2 (WDTIN = `0') 25.6 s 6.55 ms 128 (WDTIN = `1') 1.64 ms 419 ms
Reload value in WDTREL FFH 00H
Table 14 Watchdog timer range
Note
For security, rewrite WDTCON each time before the watchdog timer is serviced.
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17 Instruction Set
The table below lists the instruction set of the ST10F167. More detailed information such as address modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the "ST10 Family Programming Manual"..
Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2
Table 15 Instruction set summary
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Mnemonic ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS Description Arithmetic (sign bit) shift right direct word GPR Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Bytes 2 2/4 2/4 2/4 4 4 4 4 4 4 4
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Call absolute subroutine in any code segment
Push direct word register onto system stack & call absolute subroutine 4 Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (assumes NMI-pin low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Table 15 Instruction set summary
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18 Bootstrap Loader
The built-in bootstrap loader of the ST10F167 provides a mechanism to load the startup program through the serial interface after reset. The ST10F167 enters BSL mode when pin P0L.4 is sampled low at the end of a hardware reset. In this case the built-in bootstrap loader is activated independent of the selected bus mode. The bootstrap loader code is stored in a special Boot-ROM. No part of the standard mask ROM or Flash memory area is required. The identification byte is returned in C5H.
19 Special Function Registers
The following table lists all ST10F167 SFRs in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
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Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC b b b
Physical Address FF98h FFA0h FEA0h F0A0hE FE18h FE1Ah FE1Ch FE1Eh FF9Ah FF0Ch FF14h FF16h FF18h FF1Ah FE4Ah FE80h b FF78h FE82h b FF7Ah FE84h b FF7Ch FE86h b FF7Eh FE88h b FF80h FE8Ah b FF82h FE8Ch b FF84h
8-Bit Description Address CCh D0h 50h 50h 0Ch 0Dh 0Eh 0Fh CDh 86h 8Ah 8Bh 8Ch 8Dh 25H 40h BCh 41h BDh 42h BEh 43h BFh 44h C0h 45h C1h 46h C2h A/D Converter End of Conversion Interrupt Cont Reg A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D Converter Overrun Error Interrupt Control Reg Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Register CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Register CAPCOM Register 2 CAPCOM Register 2 Interrupt Control Register CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Register CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Register CAPCOM Register 5 CAPCOM Register 5 Interrupt Control Register CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Register
Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0XX0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
BUSCON0 b BUSCON1 b BUSCON2 b BUSCON3 b BUSCON4 b CAPREL CC0 CC0IC CC1 CC1IC CC2 CC2IC CC3 CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC
Table 16 Special function registers listed by name
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Physical Address FE8Eh b FF86h FE90h b FF88h FE92h b FF8Ah FE94h b FF8Ch FE96h b FF8Eh FE98h b FF90h FE9Ah b FF92h FE9Ch b FF94h FE9Eh b FF96h FE60h b F160hE FE62h b F162hE FE64h b F164hE FE66h b F166hE FE68h b F168hE FE6Ah b F16AhE FE6Ch 8-Bit Description Address 47h C3h 48h C4h 49h C5h 4Ah C6h 4Bh C7h 4Ch C8h 4Dh C9h 4Eh CAh 4Fh CBh 30h B0h 31h B1h 32h B2h 33h B3h 34h B4h 35h B5h 36h CAPCOM Register 7 CAPCOM Register 7 Interrupt Control Register CAPCOM Register 8 CAPCOM Register 8 Interrupt Control Register CAPCOM Register 9 CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 CAPCOM Register 11 Interrupt Control Register CAPCOM Register 12 CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 CAPCOM Register 14 Interrupt Control Register CAPCOM Register 15 CAPCOM Register 15 Interrupt Control Register CAPCOM Register 16 CAPCOM Register 16 Interrupt Control Register CAPCOM Register 17 CAPCOM Register 17 Interrupt Control Register CAPCOM Register 18 CAPCOM Register 18 Interrupt Control Register CAPCOM Register 19 CAPCOM Register 19 Interrupt Control Register CAPCOM Register 20 CAPCOM Register 20 Interrupt Control Register CAPCOM Register 21 CAPCOM Register 21 Interrupt Control Register CAPCOM Register 22 Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Name CC7 CC7IC CC8 CC8IC CC9 CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC20 CC20IC CC21 CC21IC CC22
Table 16 Special function registers listed by name
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Physical Address b F16ChE FE6Eh b F16EhE FE70h b F170hE FE72h b F172hE FE74h b F174hE FE76h b F176hE FE78h b F178hE FE7Ah b F184hE FE7Ch b F18ChE FE7Eh b b b b b b b b b F194hE FF52h FF54h FF56h FF58h FF22h FF24h FF26h FF28h FE10h b FF6Ah FE08h b F100hE 8-Bit Description Address B6h 37h B7h 38h B8h 39h B9h 3Ah BAh 3Bh BBh 3Ch BCh 3Dh C2h 3Eh C6h 3Fh CAh A9h AAh ABh ACh 91h 92h 93h 94h 08h B5h 04h 80h CAPCOM Register 22 Interrupt Control Register CAPCOM Register 23 CAPCOM Register 23 Interrupt Control Register CAPCOM Register 24 CAPCOM Register 24 Interrupt Control Register CAPCOM Register 25 CAPCOM Register 25 Interrupt Control Register CAPCOM Register 26 CAPCOM Register 26 Interrupt Control Register CAPCOM Register 27 CAPCOM Register 27 Interrupt Control Register CAPCOM Register 28 CAPCOM Register 28 Interrupt Control Register CAPCOM Register 29 CAPCOM Register 29 Interrupt Control Register CAPCOM Register 30 CAPCOM Register 30 Interrupt Control Register CAPCOM Register 31 CAPCOM Register 31 Interrupt Control Register CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 5 CAPCOM Mode Control Register 6 CAPCOM Mode Control Register 7 CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (read only) P0L Direction Control Register Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FC00h 0000h 0000h 00h
Name CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CC31IC CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 CP CRIC CSP DP0L
Table 16 Special function registers listed by name
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Physical Address b b b b b b b b b F102hE F104hE F106hE FFC2h FFC6h FFCAh FFCEh FFD2h FFD6h FE00h FE02h FE04h FE06h b b F1C0hE FF0Eh FE0Ch FE0Eh b b b b b F1C2hE F1C6hE F1CEhE F1D2hE F1D6hE FF1Eh b b b b b b b b FF00h FF02h FF04h FF06h FFC0h FFC4h FFC8h FFA2h 8-Bit Description Address 81h 82h 83h E1h E3h E5h E7h E9h EBh 00h 01h 02h 03h E0h 87h 06h 07h E1h E3h E7h E9h EBh 8Fh 80h 81h 82h 83h E0h E2h E4h D1h P0H Direction Control Register P1L Direction Control Register P1H Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register Port 7 Direction Control Register Port 8 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Port 7 Open Drain Control Register Port 8 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Reset Value 00h 00h 00h 0000h 0000h 00h 00h 00h 00h 0000h 0001h 0002h 0003h 0000h 0000h 0000h 0000h 0000h 0000h 00h 00h 00h FFFFh 00h 00h 00h 00h 0000h 0000h 00h XXXXh
Name DP0H DP1L DP1H DP2 DP3 DP4 DP6 DP7 DP8 DPP0 DPP1 DPP2 DPP3 EXICON MDC MDH MDL ODP2 ODP3 ODP6 ODP7 ODP8 ONES P0L P0H P1L P1H P2 P3 P4 P5
Table 16 Special function registers listed by name
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Physical Address b b b FFCCh FFD0h FFD4h FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh F1C4hE F038hE F03AhE F03ChE F03EhE b FF10h F030hE F032hE F034hE F036hE FE30h FE32h FE34h FE36h FF30h FF32h F17EhE F108hE FEB4h b FFB0h 8-Bit Description Address E6h E8h EAh 60h 61h 62h 63h 64h 65h 66h 67h E2h 1Ch 1Dh 1Eh 1Fh 88h 18h 19h 1Ah 1Bh 18h 19h 1Ah 1Bh 98h 99h BFh 84h 5Ah D8h Port 6 Register (8 bits) Port 7 Register (8 bits) Port 8 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port Input Threshold Control Register PWM Module Period Register 0 PWM Module Period Register 1 PWM Module Period Register 2 PWM Module Period Register 3 CPU Program Status Word PWM Module Up/Down Counter 0 PWM Module Up/Down Counter 1 PWM Module Up/Down Counter 2 PWM Module Up/Down Counter 3 PWM Module Pulse Width Register 0 PWM Module Pulse Width Register 1 PWM Module Pulse Width Register 2 PWM Module Pulse Width Register 3 PWM Module Control Register 0 PWM Module Control Register 1 PWM Module Interrupt Control Register System Startup Configuration Register (Rd. only) Serial Channel 0 Baud Rate Generator Reload Reg Serial Channel 0 Control Register Reset Value 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXh 0000h 0000h
Name P6 P7 P8 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PICON PP0 PP1 PP2 PP3 PSW PT0 PT1 PT2 PT3 PW0 PW1 PW2 PW3 PWMCON0b PWMCON1b PWMIC RP0H S0BG S0CON b b
Table 16 Special function registers listed by name
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Physical Address b FF70h FEB2h b b FF6Eh F19ChE FEB0h b FF6Ch FE12h F0B4hE FFB2h FF76h F0B2hE b FF74h F0B0hE b FF72h FE14h FE16h FF12h FE50h b b FF50h FF9Ch FE54h FE52h b FF9Eh FE56h FE40h b b FF40h FF60h FE42h b b FF42h FF62h 8-Bit Description Address B8h 59h B7h CEh 58h B6h 09h 5Ah D9h BBh 59h BAh 58h B9h 0Ah 0Bh 89h 28h A8h CEh 2Ah 29h CFh 2Bh 20h A0h B0h 21h A1h B1h Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Reset Value 0000h XXh 0000h 0000h
Name S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON b SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON b T0 T01CON T0IC T0REL T1 T1IC T1REL T2 T2CON T2IC T3 T3CON T3IC b
Serial Channel 0 Transmit Buffer Register (write only) 00h Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Control Register CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register 0000h FC00h 0000h 0000h 0000h XXXXh 0000h 0000h 0000h FA00h FC00h 0xx0h1) 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Table 16 Special function registers listed by name
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Physical Address FE44h b b FF44h FF64h FE46h b b FF46h FF66h FE48h b b FF48h FF68h F050hE b b FF20h F17AhE F054hE F052hE b F17ChE F056hE b FFACh FEAEh FFAEh b b b b b F186hE F18EhE F196hE F19EhE FF1Ch 8-Bit Description Address 22h A2h B2h 23h A3h B3h 24h A4h B4h 28h 90h BEh 2Ah 29h BFh 2Bh D6h 57h D7h C3h C7h CBh CFh 8Eh GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Control Register CAPCOM Timer 7 Interrupt Control Register CAPCOM Timer 7 Reload Register CAPCOM Timer 8 Register CAPCOM Timer 8 Interrupt Control Register CAPCOM Timer 8 Reload Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register CAN Module Interrupt Control Register X-Peripheral 1 Interrupt Control Register X-Peripheral 2 Interrupt Control Register PLL Interrupt Control Register Constant Value 0's Register (read only) Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 000Xh2) 0000h 0000h 0000h 0000h 0000h
Name T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC T7 T78CON T7IC T7REL T8 T8IC T8REL TFR WDT WDTCON XP0IC XP1IC XP2IC XP3IC ZEROS
Table 16 Special function registers listed by name
Notes 1: The system configuration is selected during reset. 2: Bit WDTR indicates a watchdog timer triggered reset. 3: The Interrupt Control Registers XPnIC, control interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
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20 Electrical Characteristics
20.1 Absolute maximum ratings
Ambient temperature under bias (TA): ST10F167................................... -40to +85 C Storage temperature (TST)................................................................... - to +150 C 65 Voltage on VDD pins with respect to ground (VSS) .................................. -0.5 to +6.5 V Voltage on any pin with respect to ground (VSS) ............................. -0.3to VDD +0.3 V Input current on any pin during overload condition................................ -10 to +10 mA Absolute sum of all input currents during overload condition...........................|100 mA| Power dissipation................................................................................................. 1.5 W
Note
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VIN20.2 Parameter interpretation
The parameters listed in the Electrical Characteristics tables represent the characteristics of the ST10F167 and its demands on the system. Where the ST10F167 logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics, is included in the "Symbol" column. Where the external system must provide signals with their respective timing characteristics to the ST10F167, the symbol "SR" for System Requirement, is included in the "Symbol" column.
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20.3 DC Characteristics
VDD = 5 V 5%, VSS = 0, fCPU = 20MHz, Reset active, TA = -40 to +85 C
Limit Values Parameter Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage, all except RSTIN and XTAL1 (TTL) Input high voltage RSTIN Input high voltage XTAL1 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Symbol min. VIL SR - 0.5 - 0.5 0.2 VDD + 0.9 0.6 VDD 0.7 VDD 0.8 VDD - 0.2 400 - max. 0.2 VDD - 0.1 2.0 VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5 0.45 V V V V V V mV V - - - - - - - IOL = 2.4 mA Unit Test Condition
VILS SR VIH SR VIH1 SR VIH2 SR VIHS SR HYS
Output low voltage VOL CC (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) VOL1 CC
-
0.45 -
V V
IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA 0.45V < VIN < VDD 0.45V < VIN < VDD 5) 8) - VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax
Output high voltage VOH CC (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs)
1)
0.9 VDD 2.4 0.9 VDD 2.4
- - - 50 - -500 -
VOH1 CC IOZ1 CC IOZ2 CC IOV
4)
- 1 1 5 250 -40 - 30
V A A mA k A A A
Input leakage current (Port 5) Input leakage current (all other) Overload current RSTIN pullup resistor Read/Write inactive current Read/Write active current ALE inactive current
4) 4)
SR
2) 3) 2)
RRST CC IRWH IRWL IALEL
Table 17 DC characteristics
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Limit Values Parameter ALE active current
4) 4)
Symbol min. IALEH IP6H IP6L
4) 4) 3) 2) 3) 2) 3)
Unit max. - -40 - -10 - 20 10 120 + 5 * fCPU 40 + 2 * fCPU 100 200 50 A A A A A A pF mA mA A A mA 500 - -500 - -100 - - - - - -
Test Condition VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax 0 V < VIN < VDD f = 1MHz TA = 25 C RSTIN = VIL fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6) VDD = 5.25 V 7) VPP < VDD at 20MHz 32-Bit programming VPP = 12V
Port 6 inactive current Port 6 active current
PORT0 configuration current
IP0H IP0L IIL
XTAL1 input current Pin capacitance 5) (digital inputs/outputs) Power supply current Idle mode supply current Power-down mode supply current VPP Read Current VPP Write Current
CC
CIO CC ICC IID IPD IPPR IPPW
VPP during Write/Read
VPP
11.4
12.6
V
Table 17 DC characteristics
Notes 1: This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2: The maximum current may be drawn while the respective signal line remains inactive. 3: The minimum current must be drawn in order to drive the respective signal line active. 4: This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. 5: Not 100% tested, guaranteed by design characterization. 6: The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. 7: This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 8: Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV < VSS-0.5V). The ab-
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solute sum of input overload currents on all port pins may not exceed 50 mA. 9: Power Down Current is to be defined.
150
[mA]
ICCmax
100
ICCtyp
IIDmax 50 IIDtyp
10 5 10 15 20 fCPU [MHz]
Figure 10 Supply/idle current as a function of operating frequency
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20.4 A/D Converter Characteristics
VDD = 5 V 5%, VSS = 0 V, TA = -40 to +85 C 4.0 V < VAREF < VDD+0.1 V, V SS-0.1 V < VAGND < VSS+0.2 V
Parameter Analog input voltage range Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Symbol VAIN SR tS tC CC CC Limit Values min. VAGND - - - - - - max. VAREF 2 tSC 14 tCC + tS + 4TCL +3 tCC / 165 - 0.25 tS / 330 - 0.25 33 LSB k k pF Unit V 1) 2) 4) 3) 4) 5) tCC in [ns] 6) 7) tS in [ns] 2) 7) 7) Test Condition
TUE CC RAREFSR RASRCSR CAIN CC
Table 18 A/D converter characteristics Sample time and conversion time of the ST10F167's ADC are programmable. The table below shows the timing calculations.
ADCON.15|14 (ADCTC) 00 01 10 11 ADCON.13|12 (ADSTC) 00 01 10 11
Conversion clock tCC TCL * 24 Reserved, do not use TCL * 96 TCL * 48
Sample clock tSC tCC tCC * 2 tCC * 4 tCC * 8
Table 19 ADC timing calculations
Notes 1: VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2: During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tSC depend on programming and can be taken from the table
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above. 3: This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the table above. 4: This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 5: TUE is tested at VAREF=5.0V, VAGND=0V, VDD=4.9V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB. 6: During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results from the programmed conversion timing. 7: Not 100% tested, guaranteed by design characterization.
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20.5 AC Characteristics
20.5.1 Test waveforms
2.4V
0.2VDD+0.9
0.2VDD+0.9
Test Points 0.2VDD-0.1 0.2VDD-0.1
0.45V
AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
Figure 11 Input output waveforms
VOH VLoad +0.1V VLoad VLoad -0.1V Timing Reference Points VOL +0.1V VOL For timing purposes a port pin is no longer floating when a 100 mV change from load voltageoccurs, butbeginsto floatwhena 100mVchangefromtheloadedV OH/VOL leveloccurs (IOH/IOL = 20 mA). VOH -0.1V
Figure 12 Float waveforms
20.5.2 Definition of internal timing
The internal operation of the ST10F167 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see Table 22).
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The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This infl uence must be taken into consideration when calculating the timings for the ST10F167.
Phase Locked Loop Operation fXTAL fCPU
TCL TCL
Direct Clock Drive fXTAL fCPU
TCL TCL
Figure 13 Generation Mechanisms for the CPU clock
20.5.3 Direct Drive
When pin P0.15 (P0H.7) is low (`0') during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula:
TC L min = 1 f XT AL *DC min
DC = duty cycle
For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: 2TCL = 1/fXTAL. The address fl oat timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL * DCmax) instead of TCLmin.
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20.5.4 Phase locked loop
When pin P0.15 (P0H.7) is high (`1') during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by 4 (i.e. fCPU = fXTAL * 4). With every fourth transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so that it remains locked to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation DN:
TCLmi n = TCL NOM * ( 1 - D N 100 ) D N = ( 4 - N 15 ) [ % ]
where N = number of consecutive TCLs and 1 < N < 40. So for a period of 3 TCLs (i.e. N = 3):
D 3 = 4 - 3 15
= 3.8% TCL mi n = TCL NOM x ( 1 - 3.8 100 ) = TCLNOM x 0.962 ( 24.1nsec@f CPU = 20MHz ) This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible.
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Max.jitter [%]
This approximated formula is valid for 1 < N < 40 and 10MHz < fCPU < 20MHz.
4 3 2 1 8
2
4
16
32
N
Figure 14 Approximated maximum PLL jitter
20.5.5 External clock drive XTAL1
VDD = 5 V 5%, VSS = 0 V, TA = -40 to +85 C
Direct Drive 1:1 Parameter Oscillator period High time Low time Rise time Fall time Symbol min. tOSCSR t1SR t2SR t3SR t4SR 50 1) 25 25 - - max. 1000 - - 10 10 min. 200 6 6 - - max. 333 - - 10 10 ns ns ns ns ns PLL 1:4 Unit
Table 20 External clock drive XTAL1
Notes 1: Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.
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t1
t3
t4
VIH2 t2
VIL
tOSC
Figure 15 External clock drive XTAL1
20.5.6 Memory cycle variables
The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed.
Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol tA tC tF Values TCL * 2TCL * (15 - ) 2TCL * (1 - )
Table 21 Memory cycle variables
20.5.7 Multiplexed Bus
VDD = 5 V 5%,VSS = 0 V, TA = -40 to +85 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)
Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE Address hold after ALE t5 t6 t7 CC CC CC 15 + tA 0 + tA 15 + tA max. - - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. TCL - 10 + tA TCL - 25 + tA TCL - 10 + tA max. - - - ns ns ns
Parameter
Symbol
Unit
Table 22 Multiplexed bus characteristics
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Max. CPU Clock = 20 MHz min. ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) t8 t9 CC CC CC CC CC CC SR SR SR SR SR SR SR CC CC CC CC SR 15 + tA -10 + tA - - 25 + tC 65 + tC - - - - 0 - 15 + tC 35 + tF 35 + tF 35 + tF -5 - tA - max. - - 5 30 - - 5 + tC 55 + tC 40 + tA + tC 60 + 2tA + tC - 35 + tF - - - - 10 - tA 45 + tC + 2tA Variable CPU Clock 1/2TCL = 1 to 20 MHz min. TCL - 10 + tA -10 + tA - - 2TCL - 25 + tC 3TCL - 10 + tC - - - - 0 - 2TCL - 35 + tC 2TCL - 15 + tF 2TCL - 15 + tF 2TCL - 15 + tF -5 - tA - max. - - 5 TCL + 5 - - 2TCL - 45 + tC 3TCL - 20 + tC 3TCL - 35 + tA + tC 4TCL - 40 + 2tA + tC - 2TCL - 15 + tF - - - - 10 - tA 3TCL - 30 + tC + 2tA ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter
Symbol
Unit
Address float after RD, WR t10 (with RW-delay) Address float after RD, WR t11 (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR t12 t13 t14 t15 t16 t17 t18 t19 t22 t23 t25
Address hold after RD, WR t27 ALE falling edge to CS CS low to Valid Data In t38 t39
Table 22 Multiplexed bus characteristics
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Max. CPU Clock = 20 MHz min. CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS t40 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t54 t56 CC CC CC CC CC SR SR CC CC CC SR SR CC CC 60 + tF 20 + tA -5 + tA - - - - 40 + tC 65 + tC 35 + tC 0 - 30 + tF 30 + tF max. - - - 0 25 15 + tC 50 + tC - - - - 30 + tF - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 3TCL - 15 + tF TCL - 5 + tA -5 + tA - - - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF max. - - - 0 TCL 2TCL - 35 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter
Symbol
Unit
Table 22 Multiplexed bus characteristics
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t5 ALE t38 CSx
t16
t25
t39
t40
A23-A16 (A15-A8) BHE t6 Read Cycle BUS
t17 Address t7
t27
t54 t19 t18
Address t10 t14 t12 t46 t48
Data In
t8 RD
t42 RdCSx
t44
t51 t52
Write Cycle BUS Address t10
t23 Data Out t56 t22
t8 WR, WRL, WRH t42 WrCSx
t44
t12 t50
t48
Figure 16 External memory cycle: multiplexed bus, with read/write delay, normal ALE
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t5 ALE t38
t16
t25
t39 CSx
t40
A23-A16 (A15-A8) BHE t6 Read Cycle BUS Address
t17 Address t7
t27
t54 t19 t18 Data In t10 t14 t12 t46 t48 t51 t52
t8 RD
t42 RdCSx
t44
Write Cycle BUS Address t10 Data Out
t23
t56 t22
t8 WR, WRL, WRH t42 WrCSx
t44
t12 t50
t48
Figure 17 External memory cycle: multiplexed bus, with read/write delay, extended ALE
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t5 ALE t38 CSx
t16
t25
t39
t40
A23-A16 (A15-A8) BHE t6 Read Cycle BUS
t17 Address t7
t27
t54 t19 t18
Address t9
Data In
t11
RD t43 RdCSx
t15 t13 t51 t52
t45
t47 t49
Write Cycle BUS Address t9 WR, WRL, WRH t43 WrCSx t49 t45
t23 Data Out t56 t11 t22
t13 t50
Figure 18 External memory cycle: multiplexed bus, no read/write delay, normal ALE
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t5 ALE t38
t16
t25
t39 CSx
t40
A23-A16 (A15-A8) BHE t6 Read Cycle BUS Address
t17 Address t7 t18 Data In
t27
t54 t19
t9 RD
t11
t15 t13 t51 t52
t43 RdCSx
t45
t47 t49
Write Cycle BUS Address Data Out
t23
t56 t9 WR, WRL, WRH t43 WrCSx t49 t45 t11 t22
t13 t50
Figure 19 External memory cycle: multiplexed bus, no read/write delay, extended ALE
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20.5.8 Demultiplexed Bus
VDD = 5 V 5%,VSS = 0 V, TA = -40 to +85 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay) Data float after RD rising edge (no RW-delay) Data valid to WR Data hold after WR t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 t24 CC CC CC CC CC CC SR SR SR SR SR SR SR CC CC 15 + tA 0 + tA 15 + tA -10 + tA 25 + tC 65 + tC - - - - 0 - - 15 + tC 15 + tF max. - - - - - - 5 + tC 55 + tC 40 + tA + tC 60 + 2tA + tC - 35 + tF 15 + tF - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. TCL - 10 + tA TCL - 25 + tA TCL - 10 + tA -10 + tA 2TCL - 25 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL - 35 + tC TCL - 10 + tF max. - - - - - - 2TCL - 45 + tC 3TCL - 20 + tC 3TCL - 35 + tA + tC 4TCL - 40 + 2tA + tC - 2TCL - 15 + tF TCL - 10 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter
Symbol
Unit
Table 23 Demultiplexed bus characteristics
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Max. CPU Clock = 20 MHz min. ALE rising edge after RD, WR t26 CC CC CC SR CC CC CC SR SR CC CC CC SR SR SR CC CC -10 + tF -2.5 + tF -5 - tA - 10 + tF 20 + tA -5 + tA - - 40 + tC 65 + tC 35 + tC 0 - - -10 + tF 10 + tF max. - - 10 - tA 45 + tC + 2tA - - - 15 + tC 50 + tC - - - - 30 + tF 5 + tF - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. -10 + tF -2.5 + tF -5 - tA - TCL - 15 + tF TCL - 5 + tA -5 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - - -10 + tF TCL - 15 + tF max. - - 10 - tA 3TCL - 30 + tC + 2tA - - - 2TCL - 35 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter
Symbol
Unit
Address hold after RD, WR t28 ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS t38 t39 t41 t42 t43 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57
Table 23 Demultiplexed bus characteristics
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t5 ALE t38 CSx
t16
t26
t39
t41
A23-A16 A15-A0 BHE t6 Read Cycle BUS (D15-D8) D7-D0 t8 RD
t17 Address
t28
t55 t20 t18 Data In
t14
t12 t42 RdCSx t46 t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t8 t22
t51 t53
t24 Data Out t57
t12 t42 WrCSx t48 t50
Figure 20 External memory cycle: demultiplexed bus, with read/write delay, normal ALE
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t5 ALE t38
t16
t26
t39 CSx
t41
A23-A16 A15-A0 BHE t6 Read Cycle BUS (D15-D8) D7-D0 t8 RD
t17 Address
t28
t55 t20 t18 Data In
t14 t12 t51 t53
t42 RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t8
t24 Data Out t57 t22
t12 t42 WrCSx t48 t50
Figure 21 External memory cycle: demultiplexed bus, with read/write delay, extended ALE
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t5 ALE t38 CSx
t16
t26
t39
t41
A23-A16 A15-A0 BHE t6 Read Cycle BUS (D15-D8) D7-D0 t9 RD t43 RdCSx
t17 Address
t28
t55 t21 t18 Data In
t15 t13 t47 t49 t51 t68
Write Cycle BUS (D15-D8) D7-D0 t9 WR, WRL, WRH t43 WrCSx t49 t22
t24 Data Out t57
t13 t50
Figure 22 External memory cycle: demultiplexed bus, no read/write delay, normal ALE
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t5 ALE t38
t16
t26
t39 CSx
t41
A23-A16 A15-A0 BHE t6 Read Cycle BUS (D15-D8) D7-D0 t9 RD
t17 Address
t28
t55 t21 t18 Data In
t15 t13 t51 t68
t43 RdCSx
t47 t49
Write Cycle BUS (D15-D8) D7-D0 t9 WR, WRL, WRH t43 WrCSx t49
t24 Data Out t57 t22
t13 t50
Figure 23 External memory cycle: demultiplexed bus, no read/write delay, extended ALE
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20.5.9 CLKOUT and READY
VDD = 5 V 5%, VSS = 0 V, TA = -40 to +85 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF
Max. CPU Clock = 20 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60 CC CC CC CC CC CC SR SR SR SR SR SR 50 20 15 - - -5 + tA 30 0 65 15 0 0 max. 50 - - 5 10 10 + tA - - - - - 0 + tc + 2tA + tF
2)
Parameter
Symbol
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL TCL - 5 TCL - 10 - - -5 + tA 30 0 2TCL + 15 15 0 0 max. 2TCL - - 5 10 10 + tA - - - - - TCL - 25 + tc + 2t A + tF
2)
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
Table 24 CLKOUT and READY
Notes 1: These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2: Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and 2tc refer to the next bus cycle, tF refers to the current bus cycle.
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Running cycle 1) t32 t30 t34 ALE t31 t33 t29
READY waitstate
MUX/Tristate 6)
CLKOUT
7)
Command RD, WR
2)
t35 Sync READY t58 Async READY
3) 5) 3)
t36
t35
3)
t36
t59
t58
3)
t59
t60
4)
t37
see 6)
Figure 24 CLKOUT and READY
Notes 1: Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2: The leading edge of the respective command depends on RW-delay. 3: READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4: READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5: If the Asynchronous READY signal does not fulfil the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfil t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6: Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7: The next external bus cycle may start here.
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20.5.10 External Bus Arbitration
= 5 V 5%, VSS = 0 V, TA = -40 to +85 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF.
VDD
Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive
Symbol t61 t62 t63 t64 t65 t66 t67 SR CC CC CC CC CC CC
Max. CPU Clock = 20 MHz min. 35 - - - -5 - -5 max. - 20 20 20 25 20 25
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 35 - - - -5 - -5 max. - 20 20 20 25 20 25
Unit ns ns ns ns ns ns ns
Table 25 External bus arbitration
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CLKOUT
t61 HOLD t63 HLDA
1)
t62 BREQ t64 CSx (On P6.x) t66 Other Signals
1) 3) 2)
Figure 25 External bus arbitration, releasing the bus
Notes 1: The ST10F167 will complete the currently running bus cycle before granting bus access. 2: This is the first possibility for BREQ to get active. 3: The CS outputs will be resistive high (pullup) after t64.
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CLKOUT
2)
t61 HOLD t62 HLDA t62 BREQ t62
1)
t63
t65 CSx (On P6.x) t67 Other Signals
Figure 26 External bus arbitration (regaining the bus)
Notes 1: This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F167 requesting the bus. 2: The next ST10F167 driven bus cycle may start here.
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DATA SHEET
ST10F167
21 Package Mechanical Data
Dim mm min A A1 A2 B C D D1 D3 e E E1 E3 L L1
K
inches ty max 4.07 min ty max 0.106 0.010 3.42 3.67 0.38 0.23 31.20 28.00 22.75 0.65 31.45 28.10 0.125 0.009 0.005 1.129 1.098 1.228 1.120 0.896 0.0231.45 28.10 1.219 1.098 1.228 1.102 0.896 0.95 0.026 0.031 0.063
0(min), 7(max)
0.25 3.17 0.22 0.13 30.95 27.90
0.315
0.144 0.015 0.009 1.238 1.106
30.95 27.90
31.20 28.00 22.75
1.238 1.106
0.65
0.80 1.60
0.037
Number of Pins
VR02061A
N1
144
Figure 27 Package Outline PQFP144 (28 x 28 mm)
22 Ordering Information
Salestype Temperature range -40C to 85C Package PQFP144 (28 x 28)
ST10F167-Q6
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DATA SHEET
ST10F167
23 Revision History
This is revision 3 of this document. The differences between rev 3 and rev 2 are as follows:
* Update of the ST logo and company name. * Re-formating of the micron symbol for correct transfer onto web. * Preliminary Data becomes Data Sheet
The differences between rev 2 and rev 1 are as follows:
"GPT1 timer input frequencies, resolution and periods" on page 28 "GPT2 timer input frequencies, resolution and period" on page 29 "PWM unit frequencies and resolution at 20MHz CPU clock" on page 31 "Synchronous baud rate and reload values" on page 35 "Watchdog timer range" on page 36 "Bootstrap Loader" on page 38 Page format of the datasheet cover changed Table added Table added Table added Table added Table added Text changed
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DATA SHEET
ST10F167
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
(R)
The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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